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Signals often transmit across different clock domains in FPGA circuit design, which may result in metastable state when asynchronous inputs have critical timing combinations. Metastable issues become a key factor in digital system design and reliability analysis. Because of no methods can meet the test of metastable, how to effectively stimulate metastable and verify the validity of metastable protection measures is becoming a key issue in FPGA testing. Here, we analyzed the metastable behavior and their relevance to digital systems, and proposed a way to test multiple clock domains based on ATE test system, through the design of the deviation between the input timing signals to stimulate metastable, and verify whether the circuit protection is valid or not. On this basis, designed the ATE test system, changed the clock interval, excited the metastable behavior successfully and verified the synchronized circuits effectively avoid the spread of metastable state.