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基于高速采樣的實(shí)時(shí)DDC架構技術(shù)
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北京航天測控技術(shù)有限公司

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Real-time DDC Architecture TechnologyBased on High-speed Sampling
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    摘要:

    近年來(lái),隨著(zhù)混合域示波器技術(shù)的發(fā)展,示波器既要實(shí)現傳統示波器的功能,又要實(shí)現頻域、調制域功能,這樣在數字域信號處理中需要實(shí)現實(shí)時(shí)數字下變頻(DDC)功能,實(shí)時(shí)DDC技術(shù)是實(shí)現示波器向頻域和調制域功能擴展的基礎,可以實(shí)現示波器的增值應用,大大擴大示波器的應用領(lǐng)域。本文根據高速信號采樣的特點(diǎn),給出了實(shí)時(shí)DDC技術(shù)架構,該架構由數字正交混頻、FIR1-FIR3濾波器、HB1-HB10濾波器組成,對于20GSa/s采樣數據流而言,最高支持1.25GSa/s I/Q數據流輸出,最低305 kSa/s I/Q數據流輸出,可滿(mǎn)足絕大多數應用場(chǎng)景。對數字正交混頻、FIR1濾波器、FIR2濾波器、FIR3濾波器、HB濾波器進(jìn)行詳細設計分析,給出了實(shí)現架構,對于FIR和HB濾波器,還給出了最佳濾波器階數及其幅頻響應曲線(xiàn)。對于數字正交混頻、FIR1-FIR3濾波器,由于其數字速率超過(guò)了FPGA正常工作時(shí)鐘范圍,通過(guò)多路并行處理的手段實(shí)現信號處理。最后使用矢量信號分析軟件對DDC的13種I/Q速率下的EVM性能進(jìn)行了評估,分別評估了載波頻率1.5GHz和3GHz的EVM性能,通過(guò)評估,EVM值大部分集中在0.5%以下,可滿(mǎn)足使用需求。

    Abstract:

    In recent years, with the development of hybrid domain oscilloscope technology, the oscilloscope not only realizes the function of traditional oscilloscope, but also the function of frequency domain and modulation domain. So it is necessary to realize the function of real-time digital down-conversion (DDC) in digital domain signal processing. Real-time DDC technology is the basis of extending the function of oscilloscope to frequency domain and modulation domain. The value-added application of oscilloscope can be realized, and the application field of oscilloscope can be greatly expanded. According to the characteristics of high-speed signal sampling, this paper presents a real-time DDC technology architecture, which consists of digital orthogonal mixing, FIR1-FIR3 filter and HB1-HB10 filter. For 20GSa/s sampled data stream, the maximum support is 1.25GSa/s I/Q data stream output and the minimum 305 kSa/s I/Q data stream output, which can satisfy most application scenarios. Then, the digital orthogonal mixing, FIR1 filter, FIR2 filter, FIR3 filter and HB filter are designed and analyzed in detail, and the implementation architecture is given. For FIR and HB filters, the optimal filter order and its amplitude-frequency response curve are also given. For digital orthogonal mixer and FIR1-FIR3 filter, signal processing is realized by means of multi-channel parallel processing because its digital rate exceeds the normal working time range of the FPGA. Finally, the EVM performance of DDC at 13 I/Q rates is evaluated by vector signal analysis software. The EVM performance of carrier frequencies of 1.5 GHz and 3 GHz is evaluated respectively. Through the evaluation, the EVM value is mostly concentrated below 0.5%, which can meet the needs of application.

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吳曉曄,胡志偉,白曉遠.基于高速采樣的實(shí)時(shí)DDC架構技術(shù)計算機測量與控制[J].,2020,28(1):255-260.

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  • 收稿日期:2019-07-24
  • 最后修改日期:2019-08-19
  • 錄用日期:2019-08-20
  • 在線(xiàn)發(fā)布日期: 2020-02-22
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