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Based on a synchronous data acquisition card project in the lab, we need to design a data shared memory After research and analysis of this project, a dual port RAM shared memory based on Avalon bus in single clock true dual port mode is designed based o n programmable logic device FPGA The purpose of designing this memory is to achieve bidirectional transmission of data between the FPGA and the host computer. In order to avoid the phenomenon of information packet loss during high speed exchange, t he key idea of the parity exchange page is used to complete the exchange of digital and time scale information of the project. Finally, we verify the functional verification of the single clock true dual port mode RAM based on Avalon bus. The results show that th e designed dual port RAM realizes digital and time scale i nformation in FPGA and computer r eal time transmission with high speed and no packet loss This design takes full advantage of FPCA's existing storage resources, reducing the complexity of circuit design and achieving efficient data transfer.